MISC r0.5.0 is defined!
Today I finished working on MISC r0.5.0, which brings in machine widening to 64-bit and 8 new registers, besides other, smaller upgrades.
The most visible change, however, is that this revision brings in a rename of the architecture. When I started working on it, I first thought that "MISC" was unique, knowing (at the time) only CISC and RISC. In one of my videos at the time, I said that I wasn't aware of an already existing "MISC."
View game pageHowever, as it turns out, there already is a rich history of an architecture called "MISC," which is why, in this revision, I renamed it to "DANGCSA," or "DANGXA" when spoken, since the "C" and the "S" kind of blend together. In free written text (like docs or posts such as this one), it will always be referred to as "DANGCSA/DANGXA." It stands for "The DANGLING Computer Superarchitecture," where the "super" carries meaning similar to the "super" in "superset," since this architecture powers the DLU's display unit, the DDU (DANGLING Display Unit) and the upcoming math unit.
DANGCSA/DANGXA now has 24 DANGLING registers, of which dr0-dr15 are general-purpose dangregs, LOC and SP remain from before, and tdr0-tdr5 are temporary dangregs.
The opcode space is back at 4 bits now, carrying 16 instructions to keep the architecture simple.
I now am putting more work into the emulator since I want to start using the architecture nearly full-time as soon as possible. I think that once I start doing that, I will discover many issues that prevent full-time usage and fix them, which will make for a better user experience. Ultimately, all this is in preparation for ASIC, which is my overarching goal. I want my architecture in my computer, my phone, my TV, my pet android, and anything else with a microprocessor in it.