Welcome to the next Hardware Sniffers post entry.
Today, the topic is the DLU, which stands for the DANGLING Logic Unit, and it is the first CPU of the MISC architecture.
The DLU consists of the following parts:
dangalu.sv: the DANGLING Arithmetic Logic Unit
dangdsu.sv: the DANGLING Sound Unit
dangddu.sv: the DANGLING Display Unit (80x25 text mode + a framebuffer mode, which some parts refer to as "gfx mode," such as Crosstalk itself)
dangdiv.sv: division logic
dangcmp.sv: a comparator
dangdec.sv: the DANGLING instruction decoder
dangmem.sv: the DANGLING memory
dangmemctrl.sv: the DANGLING memory controller
dangreg.sv: an individual DANGLING register, also referred to as a "dangreg"
regfile.sv: the DANGLING register file, which contains instances of dangregs
dangt.sv: the DANGLING timer
font.sv: a character generator
dangex.sv: the DANGLING expansion interface
dangserial.sv: UART
dangnet.sv: networking logic (over serial)
parall.sv: a parallel interface that instantiates a dangdec, a dangalu, a dangdiv, a dangcmp, and a regfile for the DDU, which uses four on its four lanes
dangbridge.sv: redirection of devices from the DLU
and finally, the top:
dlu.sv: the DANGLING Logic Unit
From this point on, "MISC's CPU" will only be referred to as "the DLU" since that carries more information.
The DLU is also the core that is emulated in the official emulator.
There is some work toward an ASIC, which is also the ultimate target. It is very expensive, so comparatively, not that much work has gone there, but here are some numbers:
As per the current DLU design with a timing closure target of 20ns:
Synthesis
235.049k standard cells over a cell area of 2.98sqmm
57.388k flip-flops over an area of 1.22sqmm, which is 41% of the cell area
56.719k two-input MUXes and 4.645k four-input MUXes over an area of 0.75sqmm, which is 25% of the cell area
12.289k buffers
940 inverters
The die
2453.6 x 2464.3um, or a 2.45mm ~square with an area of 6.05sqmm
897 standard cell rows
4.762173M placement sites at 50.06% utilization
66 IOs
Clock tree
59.904k sinks
7.023k clock buffers
10 level depth
8-9 path depth
Closure
A critical path of ~45ns, which currently fails timing with a WNS of -25.4ns (33.204k endpoints in violation)
45ns:
Synthesis
identical to the 20ns run
The die
identical to the 20ns run
Clock tree
identical to the 20ns run
Detailed routing
nets: 289.65k
all DRC violations eliminated (initial: 263.047k)
total wirelength: 14.674m
vias: 2.46117M (single-cut)
Closure
corners: 9
typical (25C; 1.8V): met; WNS: +16.5ns
slow (100C; 1.6V): failed (setup); WNS: -12.5ns (23.916k endpoints)
fast (-40C; 1.95V) failed (hold); WHS: -80ps (172 endpoints)
guaranteed across all corners: ~17.4MHz
This is the DLU today (a GDS render of a top-down view of the die)
Some additional views:
